The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, it can be suitably used for a semiconductor device having a nonvolatile memory and a manufacturing method thereof.
As electrically writable and erasable nonvolatile semiconductor memory devices, EEPROM (electrically erasable and programmable read only memory) has been used widely. These memory devices typified by a flash memory that is used widely and currently have, below the gate electrode of an MISFET thereof, a conductive floating gate electrode or trap insulating film surrounded by an oxide film. With a charge accumulation state in the floating gate or trap insulating film as memory data, these devices read it as the threshold value of a transistor. This trap insulating film is an insulating film capable of accumulating charges therein and a silicon nitride film is one example of it. By shifting the threshold value of the MISFET through injection or release of charges into or from such a charge accumulation region, it can operate as a memory element. Examples of the flash memory include a split gate cell using a MONOS (metal oxide nitride oxide semiconductor) film. Such a memory has the following advantages. Described specifically, a silicon nitride film used as the charge accumulation region is superior to a conductive floating gate film in reliability of data retention because it accumulates charges discretely. This superiority in reliability of data retention enables a reduction in the thickness of an oxide film laid on and under the silicon nitride film and therefore, a reduction in the voltage necessary for write and erase operations.
A technology related to a split gate memory is described in Japanese Unexamined Patent Application Publications Nos. 2011-40782 (Patent Document 1), 2009-54707 (Patent Document 2), 2004-221554 (Patent Document 3), 2012-94790 (Patent Document 4), and 2007-258497 (Patent Document 5).